1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design 2. Generating, simulation and debugging the test patterns for ATE manufacture testing 3. Interface with back-end physical design team to complete timing closure for test related logic 4. Interface with operation team to debug production test-vectors for wafer test and final testJob Requirements:1. BS or MS, major in EE or related discipline 2. Strong experience in ASIC logic design and verification 3. 5+ years work experience in ASIC DFT design4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability5. Good communication capability and teamwork spirit        职能类别：可测性设计工程师(DFT)关键字：芯片IC半导体DFT